1. Field of the Invention
The present invention relates to a CMOS logic gate and a fabrication method of the same, and in particular, to a CMOS logic gate having a buried channel NMOS transistor and a fabrication method of the same.
2. Description of the Conventional Art
As the VLSI (Very Large Scale Integrated Circuit) is highly integrated, the MOS type semiconductor apparatus has been widely used. Recently, the device is designed to have a channel length of 0.5 micron. The device may be deteriorated due to a hot carrier, so that the reliability of the device may be decreased.
FIG. 1 illustrates a conventional CMOS inverter. As shown in FIG. 1, the conventional CMOS inverter includes a PMOS transistor 101 for pulling up an output voltage Vout to a high level when an input voltage Vin is a low level, and a NMOS transistor 111 for pulling down the output voltage Vout to a low level when the input voltage Vin is a high level. A power voltage Vdd is applied to the source of the PMOS transistor 101, and the source of the NMOS transistor is connected with a ground terminal GND.
The NMOS transistor 111 is a surface channel NMOS ransistor.
FIG. 2 is a view for explaining the operation of the NMOS transistor 111 as shown in FIG. 1. The construction of the surface channel NMOS transistor 111 will be explained with reference to FIG. 2. In the structure of the NMOS transistor 111, gates 203 and 205 are formed on the substrate 201, and a source 211 and drain 213 are formed in the substrate 201. The gates 203 and 205 are formed of an insulation layer 203 and a gate electrode 205. A spacer 207 is formed on a lateral surface of the electrode 205 and the insulation layer 203. A surface channel 241 is formed in the substrate 201 below the insulation layer 203.
The operation of the CMOS transistor of FIG. 1 will be explained with reference to FIG. 2.
When an initial state of the output voltage Vout is a high level, and an input voltage Vin is a high level, the NMOS transistor 111 is operated, and the output voltage Vout becomes a low level. At this time, in the drain region of the NMOS transistor 111, an electric field is formed by the power voltage Vdd at the initial state (high level) of the output voltage Vout. Electrons having a high energy are implanted into the insulation layer for thereby forming a trap 221 based on the impact ionization in the drain region as shown in FIG. 2 based on the hot electron by the repeated switching operations of the electric field and gate voltage. Also an interface trap can be formed on the surface of the insulation layer 203 and the substrate 201. Part of the electrons having a high energy are implanted into the spacer 207 for thereby forming a trap. This trap forms a depletion region at the drain region 213 for thereby increasing an external resistance value of the NMOS transistor 111. Therefore, as the operation of the NMOS transistor 111 is repeatedly performed, the threshold voltage of the NMOS transistor 111 is increased due to the variation of the flat band voltage due to the insulation layer trap 221 of the drain region 213, and an external resistance is increased due to the increase of the depletion region below the spacer 207. Therefore, the performance of the NMOS transistor 111 is decreased, so that the reliability of the product is degraded, and the life span of the semiconductor apparatus is reduced.
FIG. 3 illustrates the conventional CMOS logic gate. As shown in FIG. 3, the conventional CMOS logic gate is formed of a pull up transistor 301 and a pull down transistor 311. The output voltage Vout of the CMOS logic gate is outputted at the position where the pull up transistor 301 and the pull down transistor 311 are connected each other.
The pull up transistor 301 is formed of PMOS transistors 303, 305 and 307 gate-connected by input voltages Va, Vb and Vc, and the pull down transistor 311 is formed of NMOS transistors 313, 315 and 317 gate-connected by the voltages Va, Vb and Vc. The NMOS transistors 313, 315 and 317 each are formed of a surface channel NMOS transistor.
FIGS. 4A through 4C illustrate the fabrication process of the CMOS inverter as shown in FIG. 1.
As shown in FIG. 4A, field oxide films 411, 412 and 413 are formed on the substrate 401, and a photoresist pattern 431 is formed on the substrate 401. A dopant ion 441 is implemented into the substrate 401 for thereby forming the N-well 421, and a dopant ion is implanted into the N-well 421 for controlling the threshold voltage of the PMOS transistor.
As shown in FIG. 4B, the photoresist pattern 461 is formed on the N-well 421, and the dopant ion 471 is implemented. Next, a P-well 451 is formed on a portion near the N-well 421. Thereafter, a dopant ion implantation is performed in order to control the threshold voltage of the NMOS transistor in the P-well 451.
Thereafter, the CMOS inverter as shown in FIG. 4C is formed on various processes.
In the conventional CMOS logic gate, only surface channel NMOS transistor is used. Therefore, the lift span of the NMOS transistor is decreased due to the hot electron effect. As the size of the CMOS logic gate is decreased, the hot electron effect problems are increased, so that the life span of the NMOS transistor is decreased for thereby degrading a reliability of the semiconductor apparatus.